ASIC Engr

Company: Kepler Computing
Location: San Jose
Posted on: April 3, 2025

Job Description:

ASIC Engr

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Company: Kepler Computing
Location: San Jose, CA
Position Type: Full Time
Experience: See below for details
Education: See below for details
Salary Range: $178,006 to $250,000
Rate of Pay: Employer will pay or exceed the PW as determined by DOL
Location: San Jose, CA (Telewrk Permitd)
Send Resume to: ta@keplercompute.com
Duties: ASIC Engr will: design & characterize circuits on lead process nodes & integrate into chip subsys w/ indust-std place & rte/timing anlys tools; doc specs; perf prototype constructn & checkout; modify & eval designs; devlp sols to probs utilizing formal edu & prof judgmnt; & work cross-functly w/ sys team to integrate ASIC soln results into final prod.
Edu/Exp: MS or eq in EE, Elec Mag, ME, Control Sys or rel + 3 yrs exp; or BS or eq in EE, Elec mag, ME, Control Sys or rel + 5 yrs exp: Wrk in ASIC dev cycle creating high-lvl prod specs while wrkg directly w/ ASIC Engr Lead; Wrk w/ SoC (sys on a chip) des, impln & intg w/ ASIC Engr Lead; Design micro-arch & RTL using Sys Verilog RTL to meet pwr targts, perf targts & area targts as defined by prod specs; Deploy var Place & Rte (PnR), Back End & Front End tools: Synopsys ICC/ICC2, Sysnopsys Primetime & Primetime SI, Cadence Birtuoso, Conformal, Verplex, Innologic & Stratus; Prog/script langs: Perl, Python, Tel, CIC++, Shell Script, SKILL Prog & Verilog; Use ind tools for RTL synth, PnR, timing anlys, & layout verif to des, impl, & test ASIC des; Collab w/ Prod Sys team & Prod Leads on des & intg of completed ASIC design into lrgr sys construct; RTL des using Verilog, SysVerilog, VCS,Verdi; Des partitioning, synth, placement, rte & time closure for ASICs' using Cadence/Synopsys tools; & Writing TCL/Python/Perl script to reduce des iterations & improve des prod.

Keywords: Kepler Computing, San Jose , ASIC Engr, Other , San Jose, California