Principal Verification Engineer

Company: Indiesemi
Location: San Jose
Posted on: March 24, 2025

Job Description:

indie has office locations and career opportunities across the globe.The position(s) below are for office locations excluding Quebec. For job opportunities at our Quebec office, please click here.Do you enjoy working in a creative fast-growing entrepreneurial environment? With indie you -ll never walk alone! We place high value on our teams and pursue excellence for our employees and customers!indie is empowering the Autotech revolution with next generation automotive semiconductors and software platforms. We focus on edge sensors spanning multiple modalities including LiDAR, radar, ultrasound and vision for Advanced Driver Assistance Systems (ADAS), autonomous vehicles, connected car, user experience and electrification applications.indie's Vision team develops power-efficient System-on-a-Chip (SoC) ASIC devices for the automotive market. We are seeking an experienced Principal Verification Engineer to lead verification efforts at both the block and chip level, ensuring high-quality and reliable designs.Key Responsibilities

• Develop and execute block- and chip-level verification using industry-standard UVM methodology.
• Define verification plans and methodologies to ensure comprehensive coverage.
• Design and implement test bench infrastructure.
• Develop random and constrained random test cases to validate functionality.
• Specify and collect functional and code coverage metrics.
• Support FPGA emulation teams with test case debugging.
• Collaborate with the post-silicon validation team for ASIC bring-up and characterization.Qualifications & Skills
  • Bachelor's degree in Electrical or Computer Engineering (Master's preferred).
  • 10+ years of full lifecycle experience with multiple ASIC designs.
  • Extensive experience verifying System-on-Chip (SoC) devices with embedded processors.
  • Strong hands-on experience in UVM test bench development and test sequence creation.
  • Deep understanding of SoC protocols, including AMBA, DDR memory, MIPI, I2C, SPI, and UART.
  • Expertise in random and constrained random testing using UVM methodology.
  • Proactive approach to debugging and problem-solving.
  • Strong written and verbal communication skills.Preferred Experience
    • Hands-on experience with industry-standard verification tools, protocols, and Verification IP.
    • Familiarity with power intent verification (UPF).
    • Experience with design prototyping on FPGAs.
    • Knowledge of emulation systems such as HAPS and Zebu.indie Semiconductor and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law.We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.Concerning agencies: indie Semiconductor does not accept unsolicited resumes and will not be responsible for fees related to such.
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Keywords: Indiesemi, San Jose , Principal Verification Engineer, Engineering , San Jose, California