Design Verification Engineer ( Remote)

Company: Encore Semi Llc
Location: San Jose
Posted on: February 10, 2025

Job Description:

Title: Design Verification EngineerLocation: Anywhere in USA / RemoteAbout the Team:Join the growing Encore Semi Front-End Development team to collaborate with customers to design, verify and enable various subsystems and full-chip for current and next generation ASICs and SOCs. Building on your background of SV/UVM-based Design Verification, you would join a team integrating internal and 3rd party IPs into SOCs and verifying overall functional correctness.About the Project:As a senior member of an ASIC development team, you will be responsible for building a Functional Verification environment for new designs incorporating internally developed RTL and 3rd party IPs. You will leverage your SV/UVM experience to verify interfaces and interconnect. If you have SOC Integration Verification experience implementing SV/UVM environments and stimulus, directing random stimulus and deploying a coverage-based approach, joining the Encore Semi Verification team could be for you.Minimum Qualifications:

• Experience should include creating Verification Plans from the Microarchitecture Specifications and ability to understand Verilog RTL.
• SV/UVM methodology expertise to create Verification environments and drive Functional Verification including the incorporation of internal IPs and 3rd party IPs from different suppliers.
• Experience debugging RTL simulations including waveform-based debugging.
• 5+ years of Design Verification experience including working with RTL Developers.
• Knowledge of high-speed interfaces such as PCIe, DDR, and Ethernet.Preferred Qualifications:
• Verification experience focused in any of the following areas of ASIC/SOC designs:

• Processor cores
• DSPs
• General control logic
• Experience developing Verification methodologies or environments incorporating various levels of coverage but, most importantly, functional coverage (as opposed to code or statement coverage).
• Experience with industry standard EDA tools.Education Requirements:
• Required: Bachelor's, Electrical Engineering
• Preferred: Master's, Electrical EngineeringThe anticipated annual base salary for this position is between $125,000 to $150,000, which also includes a comprehensive benefits package.Full-Time Benefits:--- 15 days of PTO per calendar year--- 10 paid Holidays per calendar year--- Comprehensive Medical Benefits: Company pays 80% of medical premium for Employee and Dependents--- Dental & Vision: Company pays 50% of Dental and Vision premiums for Employee and Dependents--- Voluntary Benefits: Dental & Vision Insurance, FSA, HSA and Gap Insurance--- Employee Assistant Program (EAP)--- 401k Traditional & Roth--- Life/AD&D and Long-Term Disability--- Tuition reimbursementEqual Opportunity Policy StatementEncore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.Our management team is dedicated to this policy with respect to recruitment, hiring, placement, promotion, transfer, training, compensation, benefits, employee activities, and general treatment during employment.
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Keywords: Encore Semi Llc, San Jose , Design Verification Engineer ( Remote), Engineering , San Jose, California