Staff Engineer, ASIC Design, Front End

Company: Conductor
Location: San Jose
Posted on: April 5, 2025

Job Description:

To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.Advancing the World's Technology TogetherOur technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future.We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities.What You'll DoProduct & Solution Planning (PSP) office is part of Samsung Semiconductor, Inc. (SSI), the industry's technology and volume leader in semiconductor products. PSP's mission is to create product and technology plans to exceed customer and market expectations and to build and realize productization strategies to provide best-in-class silicon products and solutions to our customers.We are looking for Staff ASIC designer for customized HBM Buffer Die Design to join our team in San Jose, CA. A successful candidate will be responsible for creating and deploying HBM buffer die design solution for next generation customized HBM products working with multiple engineering teams.Location: Working on site at our San Jose Headquarters 5 days per week.Reports to: Senior Director, Solution PlanningYou will collaborate with architects, ASIC front-end and Design Verification teams to understand buffer die architecture, implement and get it verified. Duties would include:

• Architecture and RTL design for customized HBM buffer die
• Interface design for maximizing bandwidth between HBM memory and logic die
• Low power design (Clock and power management), generating a UPF file and verification through multi-voltage simulations
• Scope out third-party IP requirements and solicit vendors
• Perform LINT and CDC checks
• Static Timing analysis including generating constraints
• Understanding of DFT strategies, streaming scan fabric, IEEE protocols
• Experience of synthesis, DFT, functional verification, UVM verificationWhat You Bring
  • Bachelors in Electrical Engineering or related Discipline with 10+ years related experience OR Master's 8+ years related experience OR PhD 5+ years related experience.
  • Experience in Verilog/System Verilog Programming Skills.
  • Experience in interactive and waveform debug skills.
  • Experience with low-power design and clock domain crossings.
  • Design/verification experience of interface IP such as HIF/FDI/CRIF
  • Design/verification experience of ARM Cortex system using different types of BUS.
  • Firmware design and debugging experience
  • Experience with scripting such as (Python, Perl, TCL, Shell programming)
  • You're inclusive, adapting your style to the situation and diverse global norms of our people.
  • An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
  • You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
  • Innovative and creative, you proactively explore new ideas and adapt quickly to change.What We OfferThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors-including the role's function and location, as well as the individual's knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance.This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.Equal Opportunity Employment PolicySamsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
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Keywords: Conductor, San Jose , Staff Engineer, ASIC Design, Front End, Engineering , San Jose, California