ASIC Design Verification Engineer

Company: Cisco Systems, Inc.
Location: San Jose
Posted on: April 1, 2025

Job Description:

Application Window expected to close 2/10/25Meet the TeamThe Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry.Your ImpactYou will contribute to developing Cisco's revolutionary data center solutions by designing industry-leading complex chips, with full exposure to all aspects of our systems and applications, including silicon, hardware, software, telemetry, and security. Specific responsibilities include:

• Architect, develop, and maintain block, cluster, and top-level DV environment infrastructure from scratch.
• Develop test plans and qualification tests for block and cluster level designs, including constraint random and directed stimulus.
• Ensure complete verification coverage through code and functional coverage, as well as Gate Level Simulations for RTL quality.
• Collaborate with designers, architects, and software teams to address issues during post-silicon bring-up and optimize integration and performance.
• Support testing of designs in emulation and enhance existing DV environments.Minimum Qualifications
  • Bachelor's Degree in EE, CE, or other related field with 5+ years of ASIC design verification experience.
  • 5+ years of related ASIC design verification experience.
  • Proficient in ASIC verification using UVM/System Verilog.
  • Proficient in verifying complex blocks and/or clusters for ASIC.
  • Experience building test benches from scratch, hands-on experience with System Verilog constraints, structures, and classes.
  • Scripting experience with Perl and/or Python.Preferred Qualifications
    • Master's Degree in EE or CE with 3+ years of related work experience.
    • Experience with Forwarding logic/Parsers/P4.
    • Experience with Veloce/Palladium/Zebu/HAPS.
    • Formal verification (iev/vc formal) knowledge.
    • Domain experience on one or more protocols (PCIe, Ethernet, RDMA, TCP).Why Cisco?#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference.Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. Take your next step and be you, with us!
      #J-18808-Ljbffr

Keywords: Cisco Systems, Inc., San Jose , ASIC Design Verification Engineer, Engineering , San Jose, California