PCIe Protocol Engineer (Tech Staff Engineer)

Company: SQL Pager LLC
Location: San Jose
Posted on: March 28, 2025

Job Description:

The Candidate will be an expert with 32Gbps SERDES (Serializer/Deserializer) based protocols, and must possess recent work experience with PCIe Rev.3, 4 and 5 protocol.Minimum Qualifications:

• BSEE / BSCS with 10+ years of experience.
• Knowledge of FPGA architectures is a must.
• Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios.
• Strong technical background in FPGA prototype emulation, and debug.
• Strong technical background in silicon validation, failure analysis and debug.
• Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB's using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal).
• Design with RTL coding in Verilog and VHDL is a must.
• Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools.
• Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB.
• Familiarity with the bring up and on-board debug of 32Gbps SERDES.
• Hands-on systems level design and debug experience with following high-speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol):
• PCIe Gen3/4/5.
• Experience with the PCI-SIG Compliance Tests:
• Protocol Testing.
• PCI-CV Testing.
• PHY Testing.
• Experience with the PCIe Lab Equipment:
• PCIe Analyzer.
• PCIe Exerciser.
• Strong commitment to quality and customer satisfaction.
• Excellent verbal and written communication skills in English.
• Able to travel 0-2 times annually if required.Preferred qualifications:
• Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA:
• Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMII.
• Interlaken (4.25 to 412.5 Gbps).
• OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192.
• (E,X,XGS,NG)-PON or 100G-EPON.
• Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps).
• JESD204C (6.375 to 32 Gbps).
• Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary:
• Hybrid Memory Cube.
• CPRI Rate 1 to 10+.
• Serial Rapid IO 4.1.
• Firewire.
• Litefast.
• USB 3.0.
• SATA I, II, III.
• Fiber Channel.
• CoaXpress.
• C, C++ or object-oriented programming skills is desirable.
• Knowledge and experience in embedded firmware development is desirable.
• Good understanding of embedded firmware/software development process is desirable.
• Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable.
• Knowledge of PERL/TCL scripting is desirable.
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Keywords: SQL Pager LLC, San Jose , PCIe Protocol Engineer (Tech Staff Engineer), Engineering , San Jose, California